Sollicitatievraag bij Encore Semi
- problem solving: 1) write systemverilog properties to verify a given, simple protocol. 2) compute the optimal FIFO depth given the in and out timing specs. 3) Write the RTL for a FSM then synthesize it.
- problem solving: 1) write systemverilog properties to verify a given, simple protocol. 2) compute the optimal FIFO depth given the in and out timing specs. 3) Write the RTL for a FSM then synthesize it.