Setup - The time required to setup an incoming waveform before the clock edge. Hold - The time required by the waveform to hold its value after the clock edge. What does this mean? We all know that the consequence of both of the above said violations is METASTABILITY. How metastability occurs? We all know that any logic bit (0/1/X) have different ranges of voltages. Suppose the input signal obey the voltage standard in which the following is true: 1. Logic 0 is applicable when the input signal is in the range of 0 to 0.8 V 2. Logic X is applicable when the input signal is in the range of 0.8 to 2 V 3. Logic 1 is applicable when the input signal is in the range of 2 to 3.3 V Now if I sampled the input signal between 0 to 0.8 V, the circuit will interpret it as Logic 0. Similarly, if I sampled the input signal between 2 to 3.3 V, the circuit will interpret it as Logic1. But what if, mistakenly, I sampled the signal between 0.8 to 2 V: the circuit will interpret it as neither 0 nor 1. So it is declared as X. This is metastability. Since we know that all the signals are analog in nature. It means, there is the transition in the behavior of the signal from logic 0 to logic1. Or, in other words, there will be finite non-zero time to reach from logic 0 to logic 1. Hence, in order to sample logic 1 on the input signal, the signal has to pass sufficient time to settle to at least 2V. This time is called setup time. If I sample the signal before the instant when it reaches 2V, the circuit interpret the signal as logic X and will eventually go into metastability due to setup time violation. Similar logic holds for hold time violation. If the input signal changes its state before a particular period after the clock edge, the circuit will go into hold time violation. This transient time to reach the signal from logic 0 to logic 1 depends on the stray capacitance of the load connected ahead. If the stray capacitance is more, the transient time is more. If the stray capacitance is less, the transient time is less. This stray capacitance depends on the gate management inside the flipflop (load connected). In other words, the transient time depends on the flip flop (load). Hence, the setup time is the characteristic of the flipflop connected in the path and we design our circuit based on the flipflops inside the FPGA.