Describe 3 vs 4 wire SPI implementation.

Question

Fan · Accepted Answer

Well, a more commonly used 3 wire SPI has
-Clock
-SISO
-CS
which is half duplex compared to full duplex 4 wire SPI bus.

Anon · Answer

Regular 4-line configuration: 
-- Master Out Slave In (MOSI)
-- Master In Slave Out (MISO)
-- Chip Select (CS)
-- Clock

3-line configuration:
-- MOSI
-- MISO
-- Clock

"CS" can be omitted if only 1 slave exists.

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